The "brain" of the computer is the CPU. It brings instructions from memory and carries out them. The fundamental cycle of every CPU is to bring the first instruction from memory, interpret it to decide its type and operands, execute it, and then bring, decode, and carry out following instructions. The cycle is repeated until the program comes to an end. Thus, programs are executed.
Each CPU has a particular set of instructions that it can implement. Therefore a Pentium cannot carry out SPARC programs and a SPARC cannot carry out Pentium programs. Because accessing memory to get an instruction or data word takes much longer than executing an instruction, all CPUs include some registers inside to hold key variables and temporary results. Therefore the instruction set generally contains instructions to load a word from memory into a register, and store a word from a register into memory. Other instructions merge two operands from registers, memory, or both into a result, such as adding two words and storing the result in a register or in memory.
In addition to the general registers used to hold variables and temporary results, most computers have some special registers that are visible to the programmer. One of these is the program counter, which contains the memory address of the next instruction to be obtained. After that instruction has been obtained, the program counter is updated to point to its successor.
Another register is the stack pointer, which points to the top of the current stack in memory. The stack includes one frame for each procedure that has been entered but not yet exited. A procedure's stack frame holds those input parameters, local variables, and temporary variables that are not kept in registers.
Yet another register is the PSW (Program Status Word). This register includes the condition code bits, which are set by comparison instructions, the CPU priority, the mode (user or kernel), and various other control bits. User programs may normally read the entire PSW but normally may write only some of its fields. The PSW plays an important role in system calls and I/0.
The operating system must be well-informed of all the registers. When time multiplexing the CPU, the operating system will frequently stop the running program to (re)start another one. Every time it stops a running program, the operating system must save all the registers so they can be restored when the program runs later.
For getting better performance, CPU designers have long abandoned the simple model of bringing, decoding, and implementing one instruction at a time. A lot of modern CPUs have facilities for executing more than one instruction simultaneously. For instance, a CPU might have separate fetch, decode, and execute units, so that while it was executing instruction n, it could also be decoding instruction n + 1 and fetching instruction n + 2. Such an organization is called a pipeline and is illustrated in the following figure 1(a) for a pipeline with three stages. Longer pipelines are common. In most pipeline designs, once an instruction has been fetched into the pipeline, it must be executed, even if the preceding instruction was a conditional branch that was taken. Pipelines cause compiler writers and operating system writers great headaches because they disclose the complications of the underlying machine to them.
Even more advanced than a pipeline design is a superscalar CPU, shown in the following figure 1(b). In this design, multiple execution units are present, for instance, one for integer arithmetic, one for floating-point arithmetic, and one for Boolean operations. Two or more instructions are fetched at once, decoded, and dumped into a
holding buffer until they can be implemented. As soon as an execution unit is free, it looks in the holding buffer to see if there is an instruction it can handle, and if so, it removes the instruction from the buffer and carries out it. An implication of this design is that program instructions are often executed out of order. Primarily, it is up to the hardware to make sure the result produced is the same one a sequential implementation would have produced, but an annoying amount of the complication is imposed onto the operating system, as we shall see.
The majority of CPUs, except very simple ones used in embedded systems, have two modes, kernel mode and user mode, as mentioned before. Generally, a bit in the PSW controls the mode. When running in kernel mode, the CPU can carry out every instruction in its instruction set and use every feature of the hardware. The operating system runs in kernel mode, giving it access to the complete hardware.
On the contrary, user programs run in user mode, which allows only a subset of the instructions to be carried out and a subset of the features to be accessed. Normally, all instructions involving I/O and memory protection are disallowed in user mode. Setting the PSW mode bit to enter kernel mode is also prohibited, of course.
For obtaining services from the operating system, a user program must make a system call, which traps into the kernel and invokes the operating system. The TRAP instruction switches from user mode to kernel mode and starts the operating system. When the work has been completed, control is returned to the user program at the instruction following the system call. We will explain the details of the system call mechanism later in this blog but for the time being, think of it as a special kind of procedure call instruction that has the extra property of switching from user mode to kernel mode.
It is to be noted that computers have traps other than the instruction for executing a system call. Most of the other traps are caused by the hardware to warn of an exceptional situation such as an attempt to divide by 0 or a floating-point underflow. In all cases the operating system gets control and must decide what to do. Sometimes the program must be finished with an error. Other times the error can be ignored (an underflowed number can be set to 0). Lastly, when the program has announced in advance that it wants to handle certain kinds of conditions, control can be passed back to the program to let it deal with the problem.
Tagsmemory, kernel mode, user mode
- Interrupts Revisited
- Backing Store
- Shared Libraries / Mapped Files
- Page Size
- Load Control
- DESIGN ISSUES FOR PAGING SYSTEMS
- Summary of Page Replacement Algorithms
- Simulating LRU in Software
- The Least Recently Used (LRU) Page Replacement Algorithm
- Managing Free Memory
- Hybrid Implementations / Scheduler Activations
- Modeling Multiprogramming
- Process Termination
- Process Creation
- The Model of Run Time
- THE WORLD ACCORDING TO C
- The Java Virtual Machine / Exokernels
- Virtual Machines Rediscovered
- OPERATING SYSTEM STRUCTURE
- System Calls for Process Management
- SYSTEM CALLS
- Ontogeny Recapitulates Phylogeny
- Smart Card Operating Systems
- Multithreaded and Multicore Chips
- COMPUTER HARDWARE REVIEW
- The Operating System as an Extended Machine
- WHAT IS AN OPERATING SYSTEM?
- Introduction To Operating System